Thursday, March 4, 2010

Openings@Aruba Networks Bangalore(ASIC Verification Engineer )

ASIC Verification Engineer
We are looking for Verification Engineers who will be responsible for defining the test bench environment and contributing to the development of overall verification strategy, simulation environment, and coverage methodology. The candidate will work closely with a team of chip architects and digital design engineers.

Responsibilities include:
• Define pre-silicon verification/test plan.
• Execute verification plan using SystemVerilog/Verilog using both direct and Constrained Randomized verification methodology.
• Create and debug test case both in RTL and Gate Level simulation environment.
• Define and generate assertions and functional coverage points.
• Automate verification environment using Scripts.
• Create & analyze coverage metrics to ensure completeness.

• BSEE, MSEE desired
• Minimum 5+ years of experience in ASIC design/verification
• Must possess at least 3 years work experience with SystemVerilog for verification.
• 3+ years of experience in both RTL and gate level verification and debug.
• Verification experience in the following product areas:
o High speed serial link (PCI-E, XAUI)
o DDR2/DDR3 memory controller
o High speed network or switching controller.

Please contact them directly!


Post a Comment