Wednesday, April 14, 2010

Contract Verification Engineers

Design Verification Engineers, Contract opportunities in Texas and NorthEastern US. 3+ years industry experience. US residents or valid visa required.

Key Job Functions:

Develop environments for complex functional verification and debug both
functional and environmental errors in the HDL/logic model, using
simulation tools, debug tools and programming skills, based on in-depth understanding of the architecture and HDL/logical design. Develop an automated regression infrastructure setup for functional verification of high speed processor type designs. Develop/run directed tests for current and new functional features and develop/use random excercisors, to validate functionality of processor type system designs. Debug regression fails at the RTL and gate level.
Software infrastructure for validation of architecture correctness.
Directed and Random functional test environment development and use
Experience with functional/power/performance verification using
simulation and emulation environments
Create test plans for complex IPs include multiple processors
Developing test benches in OVM, SystemVerilog and/or C++, applying
pseudo-random test generators, developing System Verilog/C/assembly tests,
analyzing coverage and design-for-test on next generation SOC chip
Knowledge with Verilog SystemVerilog, HDL, programming in Perl, C/C++,
logic simulation is a requirement. Direct experience with OVM simulation
environment is a strong plus. Knowledge of computer and peripheral
architectures is also required.



  1. I'm puzzled with lots of exercises. I was afraid I could not do the right time despite my hard work. I need a support person.

  2. It seems I'm on the right track, I hope I can do well. The result was something I did and was doing to implement it.

  3. I would like to say that this blog really convinced me to do it! Thanks, very good post. Verifications IO